The present invention relates to integrated circuits, and more particularly, to integrated circuits that combine bipolar and complementary metal-oxide semiconductor (CMOS) devices.
Two general types of digital logic circuits are bipolar transistor logic and metal-oxide-semiconductor (MOS) field-effect transistor (FET) logic. These two technologies each have unique performance characteristics which have been exploited in integrated circuits which until recently were fabricated exclusively with one approach or the other.
Originally logic circuits were fabricated based upon bipolar technology. This is because it was easier to fabricate a stable bipolar transistor than it was a MOSFET transistor in the early days of integrated circuit technology. Bipolar technology offers significant advantages in operating speed and current drive capability. MOS technology offers significant advantages in other performance areas such as functional density and power dissipation levels. Accordingly, in the early days of integrated circuit production, the bipolar approach was used for high speed and high current gates in small scale integration. Later on, the MOS approach was used to achieve relatively high functional density at very low power dissipation levels, e.g. very large scale integration (VLSI) subsystem and system functions on a single chip.
For a given type of logic family, the fabrication technology is extremely important in getting the highest performance levels possible. The principal bipolar logic families are the current mode logic (CML), which is also called emitter-coupled logic (ECL) and transistor-transistor logic (TTL). The principal MOS logic families are (1) the traditional MOS approach using exclusively p-channel or n-channel FETs to fabricate large memories and microprocessor VLSI circuits that operate at megahertz speeds (as compared with over 100 times that speed with bipolar logic); and (2) the CMOS technology using both p-channel and n-channel FETs to provide very low power digital logic functions at densities intermediate between that offered by the bipolar and traditional MOS approaches.
The MOSFET transistor can be used in various connections to perform an NAND or NOR operation. Other gates can be realized by using all p-channel devices or all n-channel devices. CMOS integrated circuits use both p-channel and n-channel FETs in a complementary push-pull arrangement. This complicates the fabrication process somewhat since both types of transistors must be fabricated on the same circuit. However, CMOS technology offer numerous significant advantages over traditional MOS technology. The transfer characteristics of a CMOS gate are superior. With CMOS logic the power supply voltage can vary significantly without disrupting proper gate operation. CMOS allows the designer to spread out the O and 1 levels to provide a larger noise margin and higher drive voltage levels. With a CMOS gate, one or the other path to ground from the power supply is open except at the exact middle of the transition region when both transistors are on. Therefore current flows from the power supply only during the brief time of transition from 0 to 1, resulting in very low power dissipation. Unfortunately, the very brief power supply current spike during transitions can be large and cause noise problems in the rest of the system.
Recently integrated circuits have become commercially available that utilize both the bipolar and CMOS approaches in the same chip in order to capitalize on the unique performance advantages of each technology. Such devices combine the short propagation delays of bipolar with low CMOS standby currents.
Previous work in the BiCMOS area has been directed to techniques where low power is achieved only with added complexity, i.e. low density, or high density is achieved at the expense of higher power resulting in undesirable crowbar current.
FIG. 1 of the drawings herein illustrates one prior art BiCMOS logic gate in the form of an inverter. A p-channel MOSFET M.sub.1 and an n-channel MOSFET M.sub.2 have their gates connected to a common input. The drain of MOSFET M.sub.1 is connected through resistor R.sub.1 to the drain of MOSFET M.sub.2 whose source is grounded through resistor R.sub.2. A pair of NPN bipolar transistors Q.sub.1 and Q.sub.2 have their bases connected to the drains of MOSFET M.sub.1 and MOSFET M.sub.2, respectively. The collector of transistor Q.sub.1 is connected to voltage source V.sub.DD. The source of MOSFET M.sub.1 is also connected to voltage source V.sub.DD. The emitter of transistor Q.sub.2 is grounded. The emitter of transistor Q.sub.1 is connected to the collector of transistor Q.sub.2 and to resistor R.sub.1 and the drain of MOSFET M.sub.2 to provide an output. This BiCMOS gate has the advantage of high density since it only has four transistors, but it suffers from high power dissipation due to substantial crowbar current of bipolar transistors Q.sub.1 and Q.sub.2. This effect is caused by transistor Q.sub.2 discharging node A through resistor R.sub.1. This develops a voltage across the base-emitter junction of transistor Q.sub.1, turning Q.sub.1 ON at the same time as Q.sub.2. This negative effect can be reduced by reducing the value of resistor R.sub.1, but this in turn slows down transistor Q.sub.1 from turning ON in the opposite case, i.e. transistor Q.sub.2 OFF, output low to high). Also the value of resistor R.sub.2 can be reduced to slow down the turning on of transistor Q.sub. 2. However, with both these techniques the output performance of the BiCMOS inverter is degraded. The problem becomes more severe as the logic function increases.
FIG. 3 illustrates a four-input NAND gate implemented in BiCMOS in accordance with the prior art approach exemplified in the BiCMOS inverter circuit of FIG. 1. In the circuit of FIG. 3, M.sub.1, M.sub.2, M.sub.3 and M.sub.4 are p-channel MOSFETs and M.sub.5, M.sub.6, M.sub.7 and M.sub.8 are n-channel MOSFETs. The series effect of MOSFETs M.sub.5 through M.sub.8 reduces the discharge rate of node A. As a voltage is developed across resistor R.sub.2 of approximatel V.sub.be, the bipolar transistor Q.sub.2 turns ON and attempts to discharge node A, turning on bipolar transistor Q.sub.1 and causing crowbar current to occur. Because of this negative effect, most attempts to develop BiCMOS logic circuitry have used the technique illustrated in the logic circuit illustrated in FIG. 2.
In the prior art BiCMOS circuit of FIG. 2, resistors R.sub.1 and R.sub.2 are eliminated, and a pair of n-channel MOSFETs M.sub.3 and M.sub.4 are connected as illustrated. The base of bipolar transistor Q.sub.1 is connected to the drain connections of MOSFETs M.sub.1 and M.sub.2. The gate of MOSFET M.sub.3 is connected to the common input signal and the gate of MOSFET M.sub.4 is connected to the base of bipolar transistor Q.sub.1. The drain of MOSFET M.sub.3 is connected to the emittercollector output connection between bipolar transistors Q.sub.1 and Q.sub.2. The base of bipolar transistor Q.sub.2 is connected to the source-drain connection of MOSFETs M.sub.3 and M.sub.4. The source of MOSFET M.sub.4 and the emitter of bipolar transistor Q.sub.2 are grounded. The approach of this prior art circuit has the advantage of eliminating the crowbar current effect of bipolar transistors Q.sub.1 and Q.sub.2. Not until node B is fully discharged will MOSFET M.sub.4 turn OFF, allowing bipolar transistor Q.sub.2 to turn ON. The disadvantage of this approach is that it results in relatively low density and/or low speed, as will be more fully appreciated by way of reference to FIG. 4.
FIG. 4 illustrates a four-input NAND gate implemented in BiCMOS in accordance with the prior art approach exemplified in the BiCMOS circuit of FIG. 2. M.sub.1 through M.sub.4 are p-channel MOSFETs. The four inseries n-channel MOSFETs X.sub.1A through X.sub.4.sub.A must be replicated in the form of another four in-series MOSFETs X.sub.1B through X.sub.4.sub.B in order for the logic to turn ON bipolar transistor Q.sub.2. This also increases the input loading capacitance for this type of logic. Clearly, because of the many transistor required, the low density of this approach is undesirable.
Further details regarding prior approaches to BiCMOS technology may be found in the following articles: "Applications of Hi-BiCMOS Technology", Hitachi Review, Vol. 35 (1986), No. 5. pp 225-230 (See in particular FIG. 3 on page 226); "Fast, low-power logic array unites CMOS and bipolar", ELECTRONIC DESIGN, Apr. 16, 1987; "TI's BiCMOS bus interface ICs slash standby current", ELECTRONIC PRODUCTS, June 15, 1987, pp 17-19; "HOW MOTOROLA MOVED BIMOS UP TO VLSI LEVELS", Electronics, July 10, 1986, pp 67-70; "Power-cell library brings high voltage to semicustom ICs", Electronic Design, June 11, 1987, pp 93-100; and "NEC's BiCMOS ARRAYS SHATTER RECORD", Electronics, Aug. 6, 1987, pp 82-83.